1. Field of the Invention
The present invention relates to a multivalued read only storage device (mask ROM) capable of storing multivalued data represented by plural bits, a method of driving the device, and a method of manufacturing the device.
2. Description of the Prior Art
Almost all the currently available read only storage devices are designed for storing binary data (one-bit data) in each memory cell.
However, in order to achieve a higher packing density, it is effective to store multivalued data, which is represented by plural bits, in each memory cell. Research on such read only storage devices adapted to store multivalued data has been carried out and several reports have been made.
FIG. 1 shows a memory cell group in one of such read only storage devices. In this read only storage device, each memory cell group is composed of four MOS (Metal-Oxide-Semiconductor) field-effect transistors (each referred to as the "MOSFET" hereinafter) TR0, TR1, TR2, and TR3 wherein storage data is written by implanting impurities in the channel regions. The impurity concentrations of the channel regions of the four MOSFET's are different from each other, so that the MOSFET's have different threshold voltages. More specifically, except for an impurity implanted in an entire active region of the substrate for adjusting the threshold voltage of the transistors, no impurity is implanted in the channel region of the MOSFET TR0, and impurities are implanted in the channel regions of the other MOSFET's TR1, TR2 and TR3 to form three different kinds of implant regions IR1, IR2 and IR3, respectively. As described above, the channel impurity concentrations of the implant regions differ from each other such that the MOSFET's TR0, TR1, TR2 and TR3 have different threshold voltages according to their respective storage data. In FIG. 1, "BL" indicates a bit line, "WL" indicates a word line, "GND" indicates a ground line, and "C" indicates a contact. The word lines WL constitute gate electrodes, the bit lines BL constitute drain electrodes and the ground line GND constitutes a source electrode.
In a method of driving the read only storage device of FIG. 1 for readout of storage data from a memory cell, a gate voltage (a biased electric potential applied to the word line WL) to be applied to a MOSFET TR0, TR1, TR2, TR3 to be selected is varied in three levels. Four-valued data is obtained by deciding as to which of the three gate voltages has caused the MOSFET to turn on. FIG. 2 shows a circuit for driving the read only storage device of FIG. 1 to read out storage data therefrom by this method. The circuit of FIG. 2 has a clock 50 which generates timing signals T1, T2, T3 of three different voltages respectively, a word line driver 51 for controlling the potentials of the word lines WL in the memory cell array S0, three latches 52, 53 and 54 for latching output from a selected memory cell, three differential amplifiers 55, 56 and 57 to which are inputted respective reference potentials Vref 1, Vref 2, and Vref 3 and output from the respective latches 52, 53 and 54, and a decoder 58. The timing signals T1-T3 of three different voltage levels are applied to a given word line WL as the gate voltage.
In view of the fact that the MOSFET's exhibit different drive powers with respect to the same gate voltage, there is another reading method using a constant gate voltage. According to this method, four-valued data is achieved by applying a constant gate voltage to the MOSFET, evaluating a voltage drop across the bit line based on the magnitude of the drain current, and comparing the value of the voltage drop with three different reference voltages. FIG. 3 shows a circuit for driving the read only storage device of FIG. 1 to read storage data out by this reading method.
The circuit of FIG. 3 has a word line driver 61 for controlling the potentials of the word lines WL in the memory cell array, three differential amplifiers 62, 63 and 64 receiving different reference voltages vref1, vref2 and Vref3 respectively as one of inputs, and a decoder 65. Resistors R1 and R2 are connected in series between each bit line BL and a power source V.sub.DD. When data is read out, the word line driver 61 applies a given voltage (gate voltage) to the word line WL. The drain current is determined corresponding to a MOSFET TR0, TR1, TR2, TR3 which is turned on by the gate voltage, and the voltage drop at a point P between the resistors R1 and R2 is determined corresponding to the drain current.The differential amplifiers 62, 63 and 64 compare a voltage at the point P with the reference voltages Vref1, Vref2 and Vref3 respectively, and the decoder 65 analyzes the outputs from the differential amplifiers 62, 63 and 64, resulting in obtainment of a four-valued data.
FIG. 4 shows a memory cell group of another read only storage device adapted to store multivalued data. As shown in FIG. 4, each memory cell group of this read only storage device has four MOSFET's TR4, TR5, TR6 and TR7 which have different channel widths to have different drive powers in correspondence with storage data. Reading of storage data from the read only storage device of FIG. 4 is executed by a circuit as shown in FIG. 3.
The aforementioned read only storage devices, however, have the following problems.
In the read only storage device shown in FIG. 1, the four MOSFET's TR0, TR1, TR2, and TR3 have different channel impurity concentrations. More specifically, the MOSFET TR0 has been subjected to no channel impurity implantation, the MOSFET TR1 has been subjected to only a first channel impurity implantation, the MOSFET TR2 has been subjected to only a second channel impurity implantation, and the MOSFET TR3 has been subjected to both the first and second channel impurity implantation. Production of the read only storage device of such an arrangement requires at least two masking (photolithography) steps and ion implantation steps in addition to the normal process of manufacturing the binary read only storage device. The increase in the number of steps of the manufacturing process causes reduction of the yield of the products. Furthermore, in manufacturing the read only storage device of FIG. 1, the channel impurity concentrations must be controlled so as to obtain threshold voltages corresponding to the four different storage data with good reproducibility. However, according to the growing trend of applying a lower voltage to the device, the margin in setting the threshold voltages reduces. For instance, in a device operating on a power voltage of 3 V, it is required to set four threshold voltages within the voltage range of about 3 V, which means that obtainment of the threshold voltages with high reproducibility is becoming more and more difficult.
When the driving method adopted in the circuit shown in FIG. 2 is used in reading storage data from the read only storage device, the gate voltage to be applied to the MOSFET TR0, TR1, TR2, TR3 is varied in three different levels (timing signals T1, T2, and T3 are applied as the three different gate voltages), which means that the gate voltage control is complicated. It is difficult to control a time to decide as to which voltage has turned the MOSFET on, and therefore it is difficult to increase the read rate. Furthermore, since the decision of the ON/OFF state of a MOSFET is effected with respect to every gate voltage (T1, T2, T3), time required for the decisions increases when the decisions are executed serially. On the other hand, when the decisions are executed in parallel, plural (three) decision circuits are required. In this case, the size of the device including the peripheral circuit becomes large.
When reading of storage data is executed by the circuit shown in FIG. 3, data are obtained by evaluating the voltage drop at the point P between the resistors R1 and R2 from the magnitude of the drain current and comparing a value of the voltage drop with the three reference voltages (Vref1, Vref2, and Vref3). In this case, the comparison cannot be executed until the dropped voltage is sufficiently stabilized, which requires a long read time. Furthermore, since the decision of data must be carried out plural (three) times, time required for the decisions increases if the decisions are executed serially. On the other hand, if the decisions are executed in parallel, plural number of decision circuits are required. This causes an increase in size of the device including the peripheral circuit.
In the case of the read only storage device shown in FIG. 4, the four MOSFET's TR4, TR5, TR6, and TR7 have different channel widths. Among the channel widths, the minimum channel width (the channel width of the MOSFET TR6) is determined by the process conditions. Since the size of the memory cell depends on the dimensions of the MOSFET TR4 having the maximum channel width, a rather great area is required for each memory cell. Therefore, even though the read only storage device stores multivalued data in each memory cell, the high integration effect is reduced. Furthermore, in the read only storage device of FIG. 4, the channel width of each MOSFET is varied according to the storage data, and the written data corresponds to the physical width of the active region. Therefore, writing of the data is carried out in the time of processing the LOCOS formation. This requires a long turnaround time for the device manufacture.
When storage data is read out from the read only storage device of FIG. 4 by the circuit as shown in FIG. 3, the same problems as described above occur.